The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized. Similar developments in IC processing and manufacturing are needed. For example, a three dimensional transistor, such as a fin-like field-effect transistor (FinFET), has been introduced to replace a planar transistor. A FinFET can be thought of as a typical planar device extruded into the gate. A typical FinFET is fabricated with a thin “fin” (or fin structure) extending up from a substrate. The channel of the FET is formed in this vertical fin, and a gate is provided over (e.g., wrapping around) the channel region of the fin. Wrapping the gate around the fin increases the contact area between the channel region and the gate and allows the gate to control the channel from multiple sides. This can be leveraged in a number of way, and in some applications, FinFETs provide reduced short channel effects, reduced leakage, and higher current flow. In other words, they may be faster, smaller, and more efficient than planar devices.
However, because of the complexity inherent in FinFETs and other nonplanar devices, and further because of the high pattern density in the advanced technology modes, a number of techniques used in manufacturing planar transistors are not well suited to fabricating nonplanar devices. As merely one example, conventional techniques for forming gate stacks on a semiconductor substrate may produce undesirable collapse or sticking issue. In the advanced technology nodes, the height of the transistor gates needs to be very higher. For example, when the gate length is less than 20 nm, the gate aspect ratio, defined as the gate height over the gate width, can be greater than 15. The high gate aspect ratio may cause adjacent gates to collapse or stick together, especially during various processes, such as wet etching and cleaning. Other concerns includes under-cutting to shallow trench isolation (STI) during source/drain epitaxy growth or over-etching to the STI during forming contacts to source and drain in various examples.
Therefore, while existing fabrication techniques have been generally adequate for planar devices, in order to continue to meet ever-increasing design requirements, further advances are needed.